Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 321)

VHDL AXI3 and AXI4 Master BFMs
get_write_response_ready_delay()
Mentor VIP AE AXI3/4 User Guide, V10.2b 303
September 2013
get_write_response_ready_delay()
This nonblocking procedure gets the write_response_ready_delay field for a transaction that is
uniquely identified by the transaction_id field previously created by the
create_write_transaction() procedure.
AXI3 Example
-- Create a write transaction with start address of 0.
-- Creation returns tr_id to identify the transaction.
create_write_transaction(0, tr_id, bfm_index, axi_tr_if_0(bfm_index));
....
-- Get the write response channel BREADY delay of the tr_id transaction.
get_write_response_ready_delay(write_resp_ready_delay, tr_id, bfm_index,
axi_tr_if_0(bfm_index));
Prototype -- * = axi| axi4
-- ** = AXI | AXI4
get_write_response_ready_delay
(
write_response_ready_delay: out integer;
transaction_id : in integer;
bfm_id : in integer;
path_id : in *_path_t; --optional
signal tr_if : inout *_vhd_if_struct_t
);
Arguments write_response_ready_delay Write data channel BREADY delay measured in ACLK
cycles for this transaction.
transaction_id Transaction identifier. Refer to “Overloaded Procedure
Common Arguments” on page 203 for more details.
bfm_id BFM identifier. Refer to “Overloaded Procedure Common
Arguments” on page 203 for more details.
path_id (Optional) Parallel process path identifier:
**_PATH_0
**_PATH_1
**_PATH_2
**_PATH_3
**_PATH_4
Refer to “Overloaded Procedure Common Arguments” on
page 203 for more details.
tr_if Transaction signal interface. Refer to “Overloaded
Procedure Common Arguments” on page 203 for more
details.
Returns write_response_ready_delay