Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 653)

VHDL Tutorials
Verifying a Master DUT
Mentor VIP AE AXI3/4 User Guide, V10.2b 633
September 2013
If the slave_mode is configured to AXI_PHASE_SLAVE (unbuffered) the code waits for a single
write data phase (beat) to complete via the get_write_data_phase procedure, in a while loop.
The address and data pairs from the transaction are obtained by the get_write_addr_data
procedure before calling the do_byte_write procedure which writes the data byte into the
memory mem at the corresponding addr address. If the number of bytes to be written (for this
beat) is more than one, then loop j writes the remaining bytes of this beat into the memory mem.
The while loop then repeats, waiting for another data phase (beat), if this is not the last data
phase (beat) in the burst.
The transaction record, so far, is then pushed onto a new transaction queue identifier
AXI_QUEUE_ID_2 by the push_transaction_id procedure, which is then ready for the slave to
execute a response back to the master (refer to
Example 11-26 ).
Example 11-26. handle_write
-- handle_write : write data phase through path 1
-- This process receives write data burst, or write phases (beats).
-- The slave_mode configuration controls when the write data is passed to
-- memory.
process
variable write_trans: integer;
variable byte_length : integer;
variable burst_length : integer;
variable addr : std_logic_vector(AXI_MAX_BIT_SIZE-1 downto 0);
variable data : std_logic_vector(7 downto 0);
variable last : integer := 0;
variable loop_i : integer := 0;
begin
loop
pop_transaction_id(write_trans, AXI_QUEUE_ID_0, index, AXI_PATH_1,
axi_tr_if_1(index));
set_write_data_ready_delay(write_trans, AXI_PATH_1,
axi_tr_if_1(index));
if (slave_mode = AXI_TRANSACTION_SLAVE) then
get_write_data_burst(write_trans, index, AXI_PATH_1,
axi_tr_if_1(index));
get_burst_length(burst_length, write_trans, index, AXI_PATH_1,
axi_tr_if_1(index));
for i in 0 to burst_length loop
get_write_addr_data(write_trans, i, 0, byte_length, addr, data,
index, AXI_PATH_1, axi_tr_if_1(index));
do_byte_write(addr, data);
if byte_length > 1 then
for j in 1 to byte_length-1 loop
get_write_addr_data(write_trans, i, j, byte_length, addr,
data, index, AXI_PATH_1, axi_tr_if_1(index));
do_byte_write(addr, data);
end loop;
end if;
end loop;
else
last := 0;
loop_i := 0;