Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 737)

SystemVerilog AXI3 and AXI4 Test Programs
SystemVerilog AXI4 Master BFM Test Program
Mentor VIP AE AXI3/4 User Guide, V10.2b 717
September 2013
bfm.execute_transaction(trans8);
if (trans8.get_data_words(0) == 'hACE0ACE1)
$display ( "@ %t, master_test_program: Read correct data (hACE0ACE1)
at address (64)", $time);
else
$display ( "@ %t, master_test_program: Error: Expected data
(hACE0ACE1) at address (64), but got %h", $time,
trans8.get_data_words(0));
if (trans8.get_data_words(1) == 'hACE2ACE3)
$display ( "@ %t, master_test_program: Read correct data (hACE2ACE3)
at address (68)", $time);
else
$display ( "@ %t, master_test_program: Error: Expected data
(hACE2ACE3) at address (68), but got %h", $time,
trans8.get_data_words(1));
if (trans8.get_data_words(2) == 'hACE4ACE5)
$display ( "@ %t, master_test_program: Read correct data (hACE4ACE5)
at address (72)", $time);
else
$display ( "@ %t, master_test_program: Error: Expected data
(hACE4ACE5) at address (72), but got %h", $time,
trans8.get_data_words(2));
#10000
$finish();
end
// Task : handle_write_resp_ready
// This method assert/de-assert the write response channel ready signal.
// Assertion and de-assertion is done based on following variable's
// value:
// m_wr_resp_phase_ready_delay
// master_ready_delay_mode
task automatic handle_write_resp_ready;
bit seen_valid_ready;
int tmp_ready_delay;
axi4_master_ready_delay_mode_e tmp_mode;
forever
begin
wait(m_wr_resp_phase_ready_delay > 0);
tmp_ready_delay = m_wr_resp_phase_ready_delay;
tmp_mode = master_ready_delay_mode;
if (tmp_mode == AXI4_VALID2READY)
begin
fork
bfm.execute_write_resp_ready(1'b0);
join_none
bfm.get_write_response_cycle;
repeat(tmp_ready_delay - 1) bfm.wait_on(AXI4_CLOCK_POSEDGE);