SystemVerilog Tutorials
Verifying a Slave DUT
Mentor VIP AE AXI3/4 User Guide, V10.2b
145
September 2013
Figure 6-3. master_ready_delay_mode = AXI4_TRANS2READY
*VALID
*READY
ACLK
*_valid_delay = 4
*_ready_delay = 2
