Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 724)

Mentor VIP AE AXI3/4 User Guide, V10.2b 704
SystemVerilog AXI3 and AXI4 Test Programs
SystemVerilog AXI3 Slave BFM Test Program
September 2013
// Enum type for slave mode
// AXI_TRANSACTION_SLAVE - Works at burst level (write data is received at
// burst and read data/response is sent in burst)
// AXI_PHASE_SLAVE - Write data and read data/response is worked upon
// at phase level
typedef enum bit
{
AXI_TRANSACTION_SLAVE = 1'b0,
AXI_PHASE_SLAVE = 1'b1
} axi_slave_mode_e;
/////////////////////////////////////////////////
// Code user could edit according to requirements
/////////////////////////////////////////////////
// Slave mode seclection : default it is transaction level slave
axi_slave_mode_e slave_mode = AXI_TRANSACTION_SLAVE;
// Slave max outstanding reads
int m_max_outstanding_read_trans = 2;
// Slave max outstanding writes
int m_max_outstanding_write_trans = 2;
// Storage for a memory
bit [7:0] mem [*];
// Function : do_byte_read
// Function to provide read data byte from memory at particular input
// address
function bit[7:0] do_byte_read(addr_t addr);
return mem[addr];
endfunction
// Function : do_byte_write
// Function to write data byte to memory at particular input address
function void do_byte_write(addr_t addr, bit [7:0] data);
mem[addr] = data;
endfunction
// Function : set_write_address_ready_delay
// This is used to set write address phase ready delay to extend phase
function void set_write_address_ready_delay(axi_transaction trans);
trans.set_address_ready_delay(1);
endfunction
// Function : set_read_address_ready_delay
// This is used to set read address phase ready delay to entend phase
function void set_read_address_ready_delay(axi_transaction trans);
trans.set_address_ready_delay(1);
endfunction