Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 84)

Mentor VIP AE AXI3/4 User Guide, V10.2b 66
SystemVerilog AXI3 and AXI4 Master BFMs
execute_write_resp_ready()
September 2013
execute_write_resp_ready()
This AXI4 task executes a write response ready by placing the ready argument value onto the
BREADY signal. It will block for one ACLK period.
AXI3 BFM
Note
The execute_write_resp_ready() task is not available in the AXI3 BFM. Use the
get_write_response_phase() task along with the transaction record
write_response_ready_delay field.
AXI4 Example
// Assert and deassert the BREADY signal
forever begin
bfm.execute_write_resp_ready(1'b0);
bfm.wait_on(AXI4_CLOCK_POSEDGE);
bfm.wait_on(AXI4_CLOCK_POSEDGE);
bfm.execute_write_resp_ready(1'b1);
bfm.wait_on(AXI4_CLOCK_POSEDGE);
end
Prototype task automatic execute_write_resp_ready
(
bit ready
);
Arguments ready The value to be placed onto the BREADY signal
Returns None