Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 746)

Mentor VIP AE AXI3/4 User Guide, V10.2b 726
SystemVerilog AXI3 and AXI4 Test Programs
SystemVerilog AXI4 Slave BFM Test Program
September 2013
forever
begin
tmp_config_num_outstanding_wr_phase =
bfm.get_config(AXI4_CONFIG_NUM_OUTSTANDING_WR_PHASE);
while ((tmp_config_num_outstanding_wr_phase >=
m_max_outstanding_write_trans) && (m_max_outstanding_write_trans > 0))
begin
bfm.wait_on(AXI4_CLOCK_POSEDGE);
tmp_config_num_outstanding_wr_phase =
bfm.get_config(AXI4_CONFIG_NUM_OUTSTANDING_WR_PHASE);
end
wait(m_wr_addr_phase_ready_delay > 0);
tmp_ready_delay = m_wr_addr_phase_ready_delay;
tmp_mode = slave_ready_delay_mode;
if (tmp_mode == AXI4_VALID2READY)
begin
fork
bfm.execute_write_addr_ready(1'b0);
join_none
bfm.get_write_addr_cycle;
repeat(tmp_ready_delay - 1) bfm.wait_on(AXI4_CLOCK_POSEDGE);
bfm.execute_write_addr_ready(1'b1);
seen_valid_ready = 1'b1;
end
else // AXI4_TRANS2READY
begin
if (seen_valid_ready == 1'b0)
begin
do
bfm.wait_on(AXI4_CLOCK_POSEDGE);
while (!((bfm.AWVALID === 1'b1) && (bfm.AWREADY === 1'b1)));
end
fork
bfm.execute_write_addr_ready(1'b0);
join_none
repeat(tmp_ready_delay) bfm.wait_on(AXI4_CLOCK_POSEDGE);
fork
bfm.execute_write_addr_ready(1'b1);
join_none
seen_valid_ready = 1'b0;
end
end
endtask