Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 770)

Mentor VIP AE AXI3/4 User Guide, V10.2b 750
VHDL AXI3 and AXI4 Test Programs
VHDL AXI4 Slave BFM Test Program
September 2013
end do_byte_read;
-- Procedure : do_byte_write
-- Procedure to write data byte to memory at particular input address
procedure do_byte_write(addr : in std_logic_vector(AXI4_MAX_BIT_SIZE-1
downto 0); data : in std_logic_vector(7 downto 0)) is
begin
mem(to_integer(addr)) := data;
end do_byte_write;
-- Procedure : set_wr_resp_valid_delay
-- This is used to set write response phase valid delay to start driving
-- write response phase after specified delay.
procedure set_wr_resp_valid_delay(id : integer; signal tr_if : inout
axi4_vhd_if_struct_t) is
begin
set_write_response_valid_delay(2, id, index, tr_if);
end set_wr_resp_valid_delay;
procedure set_wr_resp_valid_delay(id : integer; path_id : in
axi4_path_t; signal tr_if : inout axi4_vhd_if_struct_t) is
begin
set_write_response_valid_delay(2, id, index, path_id, tr_if);
end set_wr_resp_valid_delay;
-- Procedure : set_read_data_valid_delay
-- This will set the ready delays for each write data phase in a write
data
-- burst
procedure set_read_data_valid_delay(id : integer; signal tr_if : inout
axi4_vhd_if_struct_t) is
variable burst_length : integer;
begin
get_burst_length(burst_length, id, index, tr_if);
for i in 0 to burst_length loop
set_data_valid_delay(i, 10, id, index, tr_if);
end loop;
end set_read_data_valid_delay;
procedure set_read_data_valid_delay(id : integer; path_id : in
axi4_path_t; signal tr_if : inout axi4_vhd_if_struct_t) is
variable burst_length : integer;
begin
get_burst_length(burst_length, id, index, path_id, tr_if);
for i in 0 to burst_length loop
set_data_valid_delay(i, 10, id, index, path_id, tr_if);
end loop;
end set_read_data_valid_delay;
begin
-- To create pipelining in VHDL there are multiple channel path in each
API.
-- So each process will choose separate path to interact with BFM.
-- process_write : write address phase through path 0
-- This process keep receiving write address phase and push the
transaction into queue through
-- push_transaction_id API.
process