Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 661)

VHDL Tutorials
Verifying a Master DUT
Mentor VIP AE AXI3/4 User Guide, V10.2b 641
September 2013
set_read_data_valid_delay()
The set_read_data_valid_delay() procedure has two prototypes (path_id is optional), and
configures the RVALID signal to be delayed by a number of ACLK cycles with the effect of
delaying the start of a read data phase (beat) in a read data burst. The delay value of the RVALID
signal, for each read data phase, is stored in an array element of the data_valid_delay
transaction field.
Example 11-35 shows the RVALID signal delay incrementing by an ACLK cycle between each
read data phase for the length of the burst. You can edit this function to change the RVALID
signal delay for the whole read burst.
Example 11-35. set_read_data_valid_delay()
procedure set_read_data_valid_delay(id : integer; path_id : in
axi4_path_t; signal tr_if : inout axi4_vhd_if_struct_t) is
variable burst_length : integer;
begin
get_burst_length(burst_length, id, index, path_id, tr_if);
for i in 0 to burst_length loop
set_data_valid_delay(i, i, id, index, path_id, tr_if);
end loop;
end set_read_data_valid_delay;
slave_mode
A configurable slave_mode signal controls the behavior of reading and writing to the . It has
two modes AXI4_TRANSACTION_SLAVE and AXI4_PHASE_SLAVE, as shown below.
type axi4_slave_mode_e is (AXI4_TRANSACTION_SLAVE, AXI4_PHASE_SLAVE);
...
-- Slave mode seclection : default it is transaction level slave
signal slave_mode : axi4_slave_mode_e := AXI4_TRANSACTION_SLAVE;
The default AXI4_TRANSACTION_SLAVE mode “saves up” an entire data burst and modifies
the slave test program internal memory in zero time for the whole burst. Therefore, a burst read
from internal memory is buffered from the beginning of the burst to the end of the burst. The
buffered read burst data is then transmitted over the protocol signals to the master on a phase-
by-phase (beat-by-beat) basis. For a write, the data burst received over the protocol signals is
buffered from the beginning of the burst to the end of the burst. At the end of the write burst the
buffered contents are written to the internal memory.
The AXI4_PHASE_SLAVE mode updates the slave test program internal memory on each data
phase (beat). Therefore, a read from the internal memory occurs only when the read data phase
(beat) actually starts to be transmitted on the protocol signals. For a write, data is written to the
internal memory as soon as each individual write data phase (beat) is received on the protocol
signals.