Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 732)

Mentor VIP AE AXI3/4 User Guide, V10.2b 712
SystemVerilog AXI3 and AXI4 Test Programs
SystemVerilog AXI4 Master BFM Test Program
September 2013
bfm.execute_transaction(trans);
if (trans.get_data_words(0) == 32'h0002_0000)
$display ( "@ %t, master_test_program: Read correct data (2) at
address (2)", $time);
else
$display ( "@ %t, master_test_program: Error: Expected data (2) at
address 2, but got %d", $time, trans.get_data_words(0));
// Read data from address 3.
trans = bfm.create_read_transaction(3);
trans.set_size(AXI4_BYTES_1);
trans.set_id(3);
bfm.execute_transaction(trans);
if (trans.get_data_words(0) == 32'h0300_0000)
$display ( "@ %t, master_test_program: Read correct data (3) at
address (3)", $time);
else
$display ( "@ %t, master_test_program: Error: Expected data (3) at
address 3, but got %d", $time, trans.get_data_words(0));
// Read data from address 4.
trans = bfm.create_read_transaction(4);
trans.set_size(AXI4_BYTES_1);
trans.set_id(4);
bfm.execute_transaction(trans);
if (trans.get_data_words(0) == 32'h0000_0004)
$display ( "@ %t, master_test_program: Read correct data (4) at
address (4)", $time);
else
$display ( "@ %t, master_test_program: Error: Expected data (4) at
address 4, but got %d", $time, trans.get_data_words(0));
// Write data burst length of 7 to start address 16.
trans = bfm.create_write_transaction(16, 7);
trans.set_size(AXI4_BYTES_4);
trans.set_data_words('hACE0ACE1, 0);
trans.set_data_words('hACE2ACE3, 1);
trans.set_data_words('hACE4ACE5, 2);
trans.set_data_words('hACE6ACE7, 3);
trans.set_data_words('hACE8ACE9, 4);
trans.set_data_words('hACEAACEB, 5);
trans.set_data_words('hACECACED, 6);
trans.set_data_words('hACEEACEF, 7);
for(int i=0; i<8; i++)
trans.set_write_strobes(4'b1111, i);
trans.set_write_data_mode(AXI4_DATA_WITH_ADDRESS);
$display ( "@ %t, master_test_program: Writing data burst of length 7
to start address 16", $time);
bfm.execute_transaction(trans);