Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 755)

VHDL AXI3 and AXI4 Test Programs
VHDL AXI3 Master BFM Test Program
Mentor VIP AE AXI3/4 User Guide, V10.2b 735
September 2013
get_data_words(data_words, 0, tr_id, index, axi_tr_if_0(index));
if(data_words(31 downto 0) = x"ACE0ACE1") then
report "master_test_program: Read correct data (hACE0ACE1) at
address (16)";
else
report "master_test_program: Expected data (hACE0ACE1) at address
(16), but got " & integer'image(to_integer(data_words(31 downto 0)));
end if;
get_data_words(data_words, 1, tr_id, index, axi_tr_if_0(index));
if(data_words(31 downto 0) = x"ACE2ACE3") then
report "master_test_program: Read correct data (hACE2ACE3) at
address (20)";
else
report "master_test_program: Expected data (hACE2ACE3) at address
(20), but got " & integer'image(to_integer(data_words(31 downto 0)));
end if;
-- Read data burst of length 1 from address 128.
create_read_transaction(128, 1, tr_id, index, axi_tr_if_0(index));
set_size(AXI_BYTES_4, tr_id, index, axi_tr_if_0(index));
execute_transaction(tr_id, index, axi_tr_if_0(index));
get_data_words(data_words, 0, tr_id, index, axi_tr_if_0(index));
if(data_words(31 downto 0) = x"ACE0AC00") then
report "master_test_program: Read correct data (ACE0AC00) at address
(128)";
else
report "master_test_program: Expected data (ACE0AC00) at address
(128), but got " & integer'image(to_integer(data_words(31 downto 0)));
end if;
get_data_words(data_words, 1, tr_id, index, axi_tr_if_0(index));
if(data_words(31 downto 0) = x"ACE2ACE3") then
report "master_test_program: Read correct data (hACE2ACE3) at
address (132)";
else
report "master_test_program: Expected data (hACE2ACE3) at address
(132), but got " & integer'image(to_integer(data_words(31 downto 0)));
end if;
wait for 100 ns;
assert false report "NONE: End of Simulation." severity failure;
end process;
end master_test_program_a;
VHDL AXI3 Slave BFM Test Program
The following code example contains a simple AXI3 slave test program that shows the slave
BFM API being used to communicate with a master and create stimulus. This test program is
discussed further in the
VHDL Tutorials chapter.
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