Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 765)

VHDL AXI3 and AXI4 Test Programs
VHDL AXI4 Master BFM Test Program
Mentor VIP AE AXI3/4 User Guide, V10.2b 745
September 2013
report "master_test_program: Read correct data (1) at address (1)";
else
hwrite(lp, data_words(31 downto 0));
report "master_test_program: Error: Expected data (1) at address 1,
but got " & lp.all;
end if;
--Read data from address 2.
create_read_transaction(2, tr_id, index, axi_tr_if_0(index));
set_id(2, tr_id, index, axi_tr_if_0(index));
set_size(AXI_BYTES_1, tr_id, index, axi_tr_if_0(index));
execute_transaction(tr_id, index, axi_tr_if_0(index));
get_data_words(data_words, tr_id, index, axi_tr_if_0(index));
if(data_words(31 downto 0) = x"00020000") then
report "master_test_program: Read correct data (2) at address (2)";
else
hwrite(lp, data_words(31 downto 0));
report "master_test_program: Error: Expected data (2) at address 2,
but got " & lp.all;
end if;
--Read data from address 3.
create_read_transaction(3, tr_id, index, axi_tr_if_0(index));
set_id(3, tr_id, index, axi_tr_if_0(index));
set_size(AXI_BYTES_1, tr_id, index, axi_tr_if_0(index));
execute_transaction(tr_id, index, axi_tr_if_0(index));
get_data_words(data_words, tr_id, index, axi_tr_if_0(index));
if(data_words(31 downto 0) = x"03000000") then
report "master_test_program: Read correct data (3) at address (3)";
else
hwrite(lp, data_words(31 downto 0));
report "master_test_program: Error: Expected data (3) at address 3,
but got " & lp.all;
end if;
--Read data from address 4.
create_read_transaction(4, tr_id, index, axi_tr_if_0(index));
set_id(4, tr_id, index, axi_tr_if_0(index));
set_size(AXI_BYTES_1, tr_id, index, axi_tr_if_0(index));
execute_transaction(tr_id, index, axi_tr_if_0(index));
get_data_words(data_words, tr_id, index, axi_tr_if_0(index));
if(data_words(31 downto 0) = x"00000004") then
report "master_test_program: Read correct data (4) at address (4)";
else
hwrite(lp, data_words(31 downto 0));
report "master_test_program: Error: Expected data (4) at address 4,
but got " & lp.all;
end if;
-- Write data burst length of 7 to start address 16.
create_write_transaction(16, 7, tr_id, index, axi_tr_if_0(index));
data_words(31 downto 0) := x"ACE0ACE1";
set_data_words(data_words, 0, tr_id, index, axi_tr_if_0(index));
data_words(31 downto 0) := x"ACE2ACE3";