Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 692)

Mentor VIP AE AXI3/4 User Guide, V10.2b 672
Assertions
AXI3 Assertions
September 2013
Error
Code Error Name Description Property
Ref
AXI3-
60100 AXI_RID_CHANGED_BEFORE_
RREADY The value of RID has changed from its initial
value between the time RVALID was
asserted, and before RREADY was asserted. A3.2.1
AXI3-
60101 AXI_RID_UNKN RID has an X or Z value. A2.6
AXI3-
60102 AXI_RLAST_CHANGED_BEFORE_
RREADY The value of RLAST has changed from its
initial value between the time RVALID was
asserted, and before RREADY was asserted. A3.2.1
AXI3-
60103 AXI_RLAST_UNKN RLAST has an X or Z value. A2.6
AXI3-
60104 AXI_RREADY_UNKN RREADY has an X or Z value. A2.6
AXI3-
60105 AXI_RRESP_UNKN RRESP has an X or Z value. A2.6
AXI3-
60106 AXI_RUSER_CHANGED_
BEFORE_RREADY The value of RUSER has changed from its
initial value between the time RVALID was
asserted, and before RREADY was asserted. A3.2.1
AXI3-
60107 AXI_RUSER_UNKN RUSER has an X or Z value. A2.6
AXI3-
60108 AXI_RVALID_DEASSERTED_
BEFORE_RREADY RVALID has been de-asserted before
RREADY was asserted. A3.2.1
AXI3-
60109 AXI_RVALID_HIGH_ON_FIRST_
CLOCK_AFTER_RESET A slave interface must begin driving RVALID
high only at a rising clock edge after
ARESETn is HIGH. A3.1.2
AXI3-
60110 AXI_RVALID_UNKN RVALID has an X or Z value. A2.6
AXI3-
60111 AXI_UNALIGNED_ADDRESS_FOR_
EXCLUSIVE_READ Exclusive read accesses must have address
aligned to the total number of bytes in the
transaction. A7.2.4
AXI3-
60112 AXI_UNALIGNED_ADDRESS_FOR_
EXCLUSIVE_WRITE Exclusive write accesses must have address
aligned to the total number of bytes in the
transaction. A7.2.4
AXI3-
60113 AXI_UNALIGNED_ADDR_FOR_
WRAPPING_READ_BURST Wrapping bursts must have address aligned
to the start of the read transfer. A3.4.1
AXI3-
60114 AXI_UNALIGNED_ADDR_FOR_
WRAPPING_WRITE_BURST Wrapping bursts must have address aligned
to the start of the write transfer. A3.4.1
Table A-1. AXI3 Assertions (cont.)