Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM User Manual
Page 697
Assertions
AXI3 Assertions
Mentor VIP AE AXI3/4 User Guide, V10.2b
677
September 2013
Error
Code
Error Name
Description
Property
Ref
AXI3-
60176
AXI_TIMEOUT_WAITING_FOR_
WRITE_RESPONSE
Timed-out waiting for a write response.
A2.4
AXI3-
60177
AXI_TIMEOUT_WAITING_FOR_
READ_RESPONSE
Timed-out waiting for a read response.
A2.6
AXI3-
60178
AXI_TIMEOUT_WAITING_FOR_
WRITE_ADDR_AFTER_DATA
Timed-out waiting for a write address phase
to be coming after data.
A2.2
AXI3-
60179
AXI_DEC_ERR_RESP_FOR_READ
No slave at the address for this read transfer
(signalled by <AXI_DECERR>)
AXI3-
60180
AXI_DEC_ERR_RESP_FOR_WRITE
No slave at the address for this write transfer
(signalled by <AXI_DECERR>)
AXI3-
60181
AXI_SLV_ERR_RESP_FOR_READ
Slave has detected an error for this read
transfer (signalled by <AXI_SLVERR>)
AXI3-
60182
AXI_SLV_ERR_RESP_FOR_WRITE
Slave has detected an error for this write
transfer (signalled by <AXI_SLVERR>)
AXI3-
60183
AXI_MINIMUM_SLAVE_ADDRESS_
SPACE_VIOLATION
The minimum address space occupied by a
single slave device is 4 kilobytes.
A10.3.2
AXI3-
60184
AXI_ADDRESS_WIDTH_EXCEEDS_64
AXI supports up to 64-bit addressing.
A10.3.1
AXI3-
60185
AXI_READ_BURST_MAXIMUM_
LENGTH_VIOLATION
16 read data beats were seen without
RLAST.
A3.4.1
AXI3-
60186
AXI_WRITE_BURST_MAXIMUM_
LENGTH_VIOLATION
16 write data beats were seen without
WLAST.
A3.4.1
AXI3-
60187
AXI_WRITE_STROBES_LENGTH_
VIOLATION
The size of the write_strobes array in a write
transfer should match the value given by
AWLEN.
AXI3-
60188
AXI_EX_RD_WHEN_EX_NOT_ENABLED
An exclusive read should not be issued when
exclusive transactions are not enabled.
AXI3-
60189
AXI_EX_WR_WHEN_EX_NOT_
ENABLED
An exclusive write should not be issued when
exclusive transactions are not enabled.
AXI3-
60190
AXI_WRITE_TRANSFER_EXCEEDS_
ADDRESS_SPACE
This write transfer runs off the edge of the
address space defined by
AXI_ADDRESS_WIDTH.
A10.3.1
AXI3-
60191
AXI_READ_TRANSFER_EXCEEDS_
ADDRESS_SPACE
This read transfer runs off the edge of the
address space defined by
AXI_ADDRESS_WIDTH.
A10.3.1
AXI3-
60192
AXI_EXCL_RD_WHILE_EXCL_WR_IN_
PROGRESS_SAME_ID
Master starts an exclusive read burst while
exclusive write burst with same ID tag is in
progress.
A7.2.4
Table A-1. AXI3 Assertions (cont.)