Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 646)

Mentor VIP AE AXI3/4 User Guide, V10.2b 626
VHDL Tutorials
Verifying a Master DUT
September 2013
You can edit this procedure to change the WREADY signal delays.
Example 11-21. set_write_data_ready_delay()
-- Procedure : set_write_data_ready_delay
-- This will set the ready delays for each write data phase in a write data
-- burst
procedure set_write_data_ready_delay
(
id : integer;
signal tr_if : inout axi_vhd_if_struct_t
) is
variable burst_length : integer;
begin
get_burst_length(burst_length, id, index, tr_if);
for i in 0 to burst_length loop
set_data_ready_delay(i, i, id, index, tr_if);
end loop;
end set_write_data_ready_delay;
procedure set_write_data_ready_delay
(
id : integer; path_id : in axi_path_t;
signal tr_if : inout axi_vhd_if_struct_t
) is
variable burst_length : integer;
begin
get_burst_length(burst_length, id, index, path_id, tr_if);
for i in 0 to burst_length loop
set_data_ready_delay(i, i, id, index, path_id, tr_if);
end loop;
end set_write_data_ready_delay;
The set_read_data_valid_delay() procedure has two prototypes, one for multiple process threads
by providing the path_id argument. When called it configures the RVALID signal to be delayed
by a number of ACLK cycles with the effect of delaying the start of each read data phase (beat)
in a read data burst. The starting point of the delay is determined by the configuration of the
delay_mode operational transaction field (
“AXI3 BFM Delay Mode” on page 30 or details).
For each read data phase (beat) the delay value of the RVALID signal is stored in an element of
the data_valid_delay[] array for the transaction, as demonstrated in
Example 11-22 .