Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 644)

Mentor VIP AE AXI3/4 User Guide, V10.2b 624
VHDL Tutorials
Verifying a Master DUT
September 2013
The do_byte_write() procedure, when called, writes a data byte to the internal memory mem,
given an address location addr, as Example 11-18 illustrates.
You can edit this procedure to modify the way the write data is stored in the internal memory.
Example 11-18. do_byte_write()
-- Procedure : do_byte_write
-- Procedure to write data byte to memory at particular input address
procedure do_byte_write
(
addr : in std_logic_vector(AXI_MAX_BIT_SIZE-1 downto 0);
data : in std_logic_vector(7 downto 0)
) is
begin
mem(to_integer(addr)) := data;
end do_byte_write;
The set_read_address_ready_delay() procedure has two prototypes, one for multiple process
threads by providing the path_id argument. When called it configures the ARREADY handshake
signal to be delayed by a number of ACLK cycles which extends the length of the read address
phase. The starting point of the delay is determined by the configuration of the delay_mode
operational transaction field (refer to
“AXI3 BFM Delay Mode” on page 30 for details).
Example 11-19 demonstrates setting the ARREADY signal delay by 4 ACLK cycles.
You can edit this procedure to change the ARREADY signal delay.
Example 11-19. set_read_address_ready_delay()
-- Procedure : set_read_address_ready_delay
-- This is used to set read address phase ready delay to extend phase
procedure set_read_address_ready_delay
(
id : integer; signal tr_if : inout axi_vhd_if_struct_t
) is
begin
set_address_ready_delay(4, id, index, tr_if);
end set_read_address_ready_delay;
procedure set_read_address_ready_delay
(
id : integer; path_id : in axi_path_t;
signal tr_if : inout axi_vhd_if_struct_t
) is
begin
set_address_ready_delay(4, id, index, path_id, tr_if);
end set_read_address_ready_delay;