Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 775)

VHDL AXI3 and AXI4 Test Programs
VHDL AXI4 Slave BFM Test Program
Mentor VIP AE AXI3/4 User Guide, V10.2b 755
September 2013
execute_read_addr_ready(1, 1, index, AXI4_PATH_6,
axi4_tr_if_6(index));
end loop;
wait;
end process;
-- handle_write_data_ready : write data ready through path 7
-- This method assert/de-assert the write data channel ready signal.
-- Assertion and de-assertion is done based on
m_wr_data_phase_ready_delay
process
variable tmp_ready_delay : integer;
begin
wait_on(AXI4_RESET_0_TO_1, index, AXI4_PATH_7, axi4_tr_if_7(index));
wait_on(AXI4_CLOCK_POSEDGE, index, AXI4_PATH_7, axi4_tr_if_7(index));
loop
wait until m_wr_data_phase_ready_delay > 0;
tmp_ready_delay := m_wr_data_phase_ready_delay;
execute_write_data_ready(0, 1, index, AXI4_PATH_7,
axi4_tr_if_7(index));
get_write_data_cycle(index, AXI4_PATH_7, axi4_tr_if_7(index));
if(tmp_ready_delay > 1) then
for i in 0 to tmp_ready_delay-2 loop
wait_on(AXI4_CLOCK_POSEDGE, index, AXI4_PATH_7,
axi4_tr_if_7(index));
end loop;
end if;
execute_write_data_ready(1, 1, index, AXI4_PATH_7,
axi4_tr_if_7(index));
end loop;
wait;
end process;
end slave_test_program_a;