Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 682)

Mentor VIP AE AXI3/4 User Guide, V10.2b 662
Getting Started with Qsys and the BFMs
Setting Up Simulation from the Windows GUI
September 2013
Example Script Processing
After starting one of the example scripts from Table 12-1 , the script compiles the Mentor VIP
AE BFM for AXI3, then invokes two tcl aliases—dev_com and com to compile the required
design files. These alias commands are defined in the msim_setup.tcl simulation script
generated by Qsys along with the simulation model files.
Next, vlog compiles the three test programs:
•
master_test_program.sv
•
slave_test_program.sv
•
monitor_test_program.sv
The script then uses vlog again to compile the top.sv. Simulation starts with the elab alias.
set TOP_LEVEL_NAME top
set QSYS_SIMDIR simulation
source $QSYS_SIMDIR/mentor/msim_setup.tcl
if {![info exists env(MENTOR_VIP_AE)]} {
set env(MENTOR_VIP_AE)\
$env(QUARTUS_ROOTDIR)/../ip/altera/mentor_vip_ae
}
ensure_lib libraries
ensure_lib libraries/work
vmap work libraries/work
vlog -work work -sv \
$env(MENTOR_VIP_AE)/common/questa_mvc_svapi.svh \
$env(MENTOR_VIP_AE)/axi3/bfm/mgc_common_axi3.sv \
$env(MENTOR_VIP_AE)/axi3/bfm/mgc_axi3_monitor.sv \
$env(MENTOR_VIP_AE)/axi3/bfm/mgc_axi3_inline_monitor.sv \
$env(MENTOR_VIP_AE)/axi3/bfm/mgc_axi3_master.sv \
$env(MENTOR_VIP_AE)/axi3/bfm/mgc_axi3_slave.sv
# Compile device library files
dev_com
# Compile Qsys-generated design files
com
# Compile example test program files
vlog master_test_program.sv
vlog slave_test_program.sv
vlog monitor_test_program.sv
# Compile top-level design file
vlog top.sv
# Simulate
elab