Chapter 4 systemverilog axi3 and axi4 slave bfms, Slave bfm protocol support, Slave timing and events – Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM User Manual
Page 87
Mentor VIP AE AXI3/4 User Guide, V10.2b
69
September 2013
Chapter 4
SystemVerilog AXI3 and AXI4 Slave BFMs
This section provides information about the SystemVerilog AXI3 and AXI4 slave BFMs. Each
BFM has an API that contains tasks and functions to configure the BFM and to access the
dynamic
during the lifetime of the transaction.
Note
Due to AXI3 protocol specification changes, for some BFM tasks, you reference the
AXI3 BFM by specifying AXI instead of AXI3.
Slave BFM Protocol Support
This section defines protocol support for various AXI BFMs.
The AXI3 slave BFM supports the AMBA AXI3 protocol with restrictions described in
on page 1. In addition to the standard protocol, it supports user sideband
signals AWUSER and ARUSER.The AXI4 slave BFM supports the AMBA AXI4-Lite protocol
with restrictions described in
Slave Timing and Events
For detailed timing diagrams of the protocol bus activity refer to the relevant AMBA AXI
Protocol Specification chapter, which you can use to reference details of the following slave
BFM API timing and events.
The specification does not define any timescale or clock period with signal events sampled and
driven at rising ACLK edges. Therefore, the slave BFM does not contain any timescale,
timeunit, or timeprecision declarations with the signal setup and hold times specified in units of
simulator time-steps.
The simulator time-step resolves to the smallest of all the time-precision declarations in the
testbench and design IP based on using the directives, declarations, options, and initialization
files below:
•
` timescale directives in design elements.
•
timeprecision declarations in design elements.
•
compiler command-line options.
•
simulation command-line options