Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 640)

Mentor VIP AE AXI3/4 User Guide, V10.2b 620
VHDL Tutorials
Verifying a Slave DUT
September 2013
The set_data_words() procedure is then called four times to set the data_words field of the
write transaction for each beat of the data burst. For this write transaction, all data byte lanes
contain valid data on each beat of the data burst, therefore a ‘for’ loop calls the
set_write_strobes() procedure to set the write_strobes fields of the transaction to 15.
The call to the set_write_data_mode() procedure configures the address phase to occur before
the start of the data burst when the transaction is executed by setting the write_data_mode
transaction field to be AXI4_DATA_AFTER_ADDRESS. The call to the
set_operation_mode()
procedure configures the transaction to be nonblocking by setting the operation_mode field to
AXI4_TRANSACTION_NON_BLOCKING.
The write transaction is then executed onto the protocol signals by calling the
execute_transaction() procedure. The executed transaction will be nonblocking allowing
subsequent address phase transactions to be executed before the current write data burst has
completed. This allows outstanding write transaction stimulus to be created.
Example 11-14. Outstanding Write Burst Transaction Creation and Execution
create_write_transaction(0, 3, tr_id, index, axi4_tr_if_0(index));
data_words(31 downto 0) := x"ACE0ACE1";
set_data_words(data_words, 0, tr_id, index, axi4_tr_if_0(index));
data_words(31 downto 0) := x"ACE2ACE3";
set_data_words(data_words, 1, tr_id, index, axi4_tr_if_0(index));
data_words(31 downto 0) := x"ACE4ACE5";
set_data_words(data_words, 2, tr_id, index, axi4_tr_if_0(index));
data_words(31 downto 0) := x"ACE6ACE7";
set_data_words(data_words, 3, tr_id, index, axi4_tr_if_0(index));
for i in 0 to 3 loop
set_write_strobes(15, i, tr_id, index, axi4_tr_if_0(index));
end loop;
set_write_data_mode(AXI4_DATA_AFTER_ADDRESS, tr_id, index,
axi4_tr_if_0(index));
set_operation_mode(AXI4_TRANSACTION_NON_BLOCKING, tr_id, index,
axi4_tr_if_0(index));
execute_transaction(tr_id, index, axi4_tr_if_0(index));
Subsequent write transaction are created and executed in a similar manner to that shown in
Example 11-2 . See VHDL AXI4 Master BFM Test Program listing for details.
handle_write_resp_ready
The handle write response ready process handles the BREADY signal for the write response
channel. The whole process runs concurrently with other processes in the test program, using
the path_id = AXI4_PATH_5 (see
Overloaded Procedure Common Arguments for details of
path_id), as shown in the Example 11-15 .
The initial wait for the ARESETn signal to be deactivated, followed by a positive ACLK edge,
satisfies the protocol requirement detailed in section A3.1.2 of the Protocol Specification.