Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 215)

VHDL API Overview
Operational Transaction Fields
Mentor VIP AE AXI3/4 User Guide, V10.2b 197
September 2013
get*()
For example, a slave BFM test program uses a received write address phase to get the AWPROT
signal value from the
Transaction Record , as shown in the slave BFM test program code below.
-- * = axi| axi4
-- Wait for a write address phase;
get_write_addr_phase(slave_trans, bfm_index, *axi_tr_if_0(bfm_index));
...
-- Get the AWPROT signal value of the slave transaction
get_prot(prot_value, slave_trans, bfm_index, *axi_tr_if_0(bfm_index));
In the above example, the bfm_index specifies the BFM.
Operational Transaction Fields
Operational transaction fields control the way in which a transaction is executed on the protocol
signals. They also provide an indicator of when a data phase (beat) or transaction is complete.
Automatic Correction of Byte Lane Strobes
The master BFM permits unaligned and narrow write transfers by using byte lane strobe
(WSTRB) signals to indicate which byte lanes contain valid data per data phase (beat).
When you create a write transaction in your master BFM test program, the write_strobes
variable is available to store the write strobe values for each write data phase (beat) in the
transaction. To assist you in creating the correct byte lane strobes automatic correction of any
previously set write_strobes is performed by default during execution of the write transaction,
or write data phase (beat). You can disable this default behavior by setting the transaction field
gen_write_strobes = 0, which allows any previously set write_strobes to pass through
uncorrected onto the protocol WSTRB signals. In this mode, with the automatic correction
disabled, you are responsible for setting the correct write_strobes for the whole transaction.
The automatic correction algorithm performs a bit-wise AND operation on any previously set
write_strobes. To do the corrections, the automatic correction algorithm uses the equations
described in the AMBA AXI Protocol Specification, version 2.0, section A3.4.1, that define
valid write data byte lanes for legal protocol. Therefore, if you require automatic generation of
all write_strobes, before the write transaction executes, you must set all write_strobes to 1,
indicating that all bytes lanes initially contain valid write data, prior to execution of the write
transaction. Automatic correction will then set the relevant write_strobes to 0 to produce legal
protocol WSTRB signals.
For example, Figure Figure 7-2 below demonstrates byte lanes that can contain valid data for a
write transaction that has a start address = 0x01, size = 0b001 (2 bytes), type = INCR and length
= 0b0010 (3 beats), for a 32-bit write data bus.