Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 64)

Mentor VIP AE AXI3/4 User Guide, V10.2b 46
SystemVerilog AXI3 and AXI4 Master BFMs
create_write_transaction()
September 2013
AXI3 Example
// Create a write transaction with a data burst length of 3 (4 beats) to
// start address 16.
trans = bfm.create_write_transaction(16, 3);
trans.set_size = (AXI_BYTES_4);
trans.set_data_words = ('hACE0ACE1, 0);
trans.set_data_words = ('hACE2ACE3, 1);
trans.set_data_words = ('hACE4ACE5, 2);
trans.set_data_words = ('hACE6ACE7, 3);
AXI4 Example
// Create a write transaction with a data burst length of 3 to start
// address 16.
trans = bfm.create_write_transaction(16, 3);
trans.set_size = (AXI4_BYTES_4);
trans.set_data_words = ('hACE0ACE1, 0);
trans.set_data_words[= ('hACE2ACE3, 1);
trans.set_data_words = ('hACE4ACE5, 2);
trans.set_data_words = ('hACE6ACE7, 3);
Operational
Transaction
Fields
address_valid_delay Address channel AWVALID delay measured in ACLK cycles for
this transaction (default = 0).
data_valid_delay Write data channel WVALID delay array measured in ACLK
cycles for this transaction (default = 0 for all elements).
write_response_
ready_delay Write response channel BREADY delay measured in ACLK
cycles for this transaction (default = 0).
data_beat_done Write data channel beat done flag array for this transaction.
transaction_done Write transaction done flag for this transaction.
Returns
The *_transaction record.