Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 648)

Mentor VIP AE AXI3/4 User Guide, V10.2b 628
VHDL Tutorials
Verifying a Master DUT
September 2013
You can edit this procedure to change the BREADY signal delay.
Example 11-23. set_wr_resp_valid_delay()
-- Procedure : set_wr_resp_valid_delay
-- This is used to set write response phase valid delay to start driving
-- write response phase after specified delay.
procedure set_wr_resp_valid_delay
(
id : integer; signal tr_if : inout axi_vhd_if_struct_t
) is
begin
set_write_response_valid_delay(0, id, index, tr_if);
end set_wr_resp_valid_delay;
procedure set_wr_resp_valid_delay
(
id : integer; path_id : in axi_path_t;
signal tr_if : inout axi_vhd_if_struct_t
) is
begin
set_write_response_valid_delay(0, id, index, path_id, tr_if);
end set_wr_resp_valid_delay;
There is a slave_mode transaction field that you can configure to control the behavior of reading
and writing to the internal memory . It has two modes: AXI_TRANSACTION_SLAVE and
AXI_PHASE_SLAVE (refer to Example 11-24 ).
Example 11-24. slave_mode
-- Slave mode type definition
type axi_slave_mode_e is (AXI_TRANSACTION_SLAVE, AXI_PHASE_SLAVE);
-- Slave mode selection : Default is transaction-level slave
signal slave_mode : axi_slave_mode_e := AXI_TRANSACTION_SLAVE;
The default AXI_TRANSACTION_SLAVE mode “saves up” an entire data burst and modifies
the Slave Test Program’s internal memory in zero time for the whole burst. Therefore, a read
from internal memory is buffered at the beginning of the read burst for the whole burst. The
buffered read data is then transmitted over the protocol signals to the master on a phase-by-
phase (beat-by-beat) basis. For a write, the write data burst is buffered on a phase-by-phase
(beat-by-beat) basis for the whole burst. Only at the end of the write burst are the buffered
contents written to the internal memory.
The AXI_PHASE_SLAVE mode changes the Slave Test Program internal memory on each data
phase (beat). Therefore, a read from the internal memory occurs only when the read data phase
(beat) actually starts on the protocol signals. For a write, data is written to the internal memory
as soon as each individual write data phase (beat) completes.