Slave bfm configuration, Table 4-1. slave bfm signal width parameters – Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM User Manual

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Mentor VIP AE AXI3/4 User Guide, V10.2b

70

SystemVerilog AXI3 and AXI4 Slave BFMs
Slave BFM Configuration

September 2013

local or site-wide simulator initialization files.

If there is no timescale directive, the default time unit and time precision are tool specific. Using
timeunit and timeprecision declarations are recommended. Refer to the SystemVerilog LRM
section 3.14 for details.

Slave BFM Configuration

The slave BFM supports the full range of signals defined for the AMBA AXI protocol
specification. It has parameters you can use to configure the widths of the address, ID and data
signals, and transaction fields to configure timeout factors, slave exclusive support, and setup
and hold times, etc.

You can change the address, ID and data signal widths from their default settings by assigning
them with new values, usually performed in the top-level module of the testbench. These new
values are then passed into the slave BFM using a parameter port list of the slave BFM module.
For example, the code extract below shows the AXI3 slave BFM with the address, ID and data
signal widths defined in module top() and passed in to the slave BFM mgc_axi_slave parameter
port list:

module top ();

parameter AXI_ADDRESS_WIDTH = 24;
parameter AXI_RDATA_WIDTH = 16;
parameter AXI_WDATA_WIDTH = 16;
parameter AXI_ID_WIDTH = 4;

mgc_axi_slave #(AXI_ADDRESS_WIDTH, AXI_RDATA_WIDTH, AXI_WDATA_WIDTH,

AXI_ID_WIDTH) bfm_slave(....);

Note

In the above code extract, mgc_axi_slave is an AXI3 slave BFM interface.

Table 4-1

lists the parameter names for the address, ID and data signals, and their default

values.

Table 4-1. Slave BFM Signal Width Parameters

Signal Width Parameter

Description

**_ADDRESS_WIDTH

Address signal width in bits. This applies to the ARADDR and
AWADDR signals. Refer to the AMBA AXI Protocol
specification for more details. Default: 32

**_RDATA_WIDTH

Read data signal width in bits. This applies to the RDATA
signals. Refer to the AMBA AXI Protocol specification for more
details. Default: 64.

**_WDATA_WIDTH

Write data signal width in bits. This applies to the WDATA
signals. Refer to the AMBA AXI Protocol specification for more
details. Default: 64.

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