Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 185)

SystemVerilog Tutorials
Verifying a Master DUT
Mentor VIP AE AXI3/4 User Guide, V10.2b 167
September 2013
Example 6-31. handle_write
// Task : handle_write
// This method receive write data burst or phases for write
// transaction depending upon slave working mode, write data to
// memory and then send response
task automatic handle_write(input axi_transaction write_trans);
addr_t addr[];
bit [7:0] data[];
bit last;
set_write_data_ready_delay(write_trans);
if (slave_mode == AXI_TRANSACTION_SLAVE)
begin
bfm.get_write_data_burst(write_trans);
for( int i = 0; bfm.get_write_addr_data(write_trans,
i, addr, data); i++ )
begin
for (int j = 0; j < addr.size(); j++)
do_byte_write(addr[j], data[j]);
end
end
else
begin
for(int i = 0; (last == 1'b0); i++)
begin
bfm.get_write_data_phase(write_trans, i, last);
void'(bfm.get_write_addr_data(write_trans, i, addr, data));
for (int j = 0; j < addr.size(); j++)
do_byte_write(addr[j], data[j]);
end
end
set_wr_resp_valid_delay(write_trans);
bfm.execute_write_response_phase(write_trans);
endtask