Set_write_response_ready_delay(), Axi3 example, Axi4 bfm – Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM User Manual

Page 320

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Mentor VIP AE AXI3/4 User Guide, V10.2b

302

VHDL AXI3 and AXI4 Master BFMs
set_write_response_ready_delay()

September 2013

set_write_response_ready_delay()

This AXI3 nonblocking procedure sets the write_response_ready_delay field for a transaction
that is uniquely identified by the transaction_id field previously created by the

create_write_transaction()

procedure.

AXI3 Example

-- Create a write transaction with start address of 0.
-- Creation returns tr_id to identify the transaction.
create_write_transaction(0, tr_id, bfm_index, axi_tr_if_0(bfm_index));

-- Set the write response channel BREADY delay to 3 ACLK cycles
-- of the tr_id transaction.
set_write_response_ready_delay(3, tr_id, bfm_index,
axi_tr_if_0(bfm_index));

AXI4 BFM

Note

This procedure is not supported in the AXI4 BFM API.

Prototype

set_write_response_ready_delay
(

write_response_ready_delay: in integer;
transaction_id : in integer;
bfm_id : in integer;
path_id : in axi_path_t; --optional
signal tr_if : inout axi_vhd_if_struct_t

);

Arguments

write_response_ready_delay Write data channel BREADY delay measured in ACLK

cycles for this transaction. Default: 0.

transaction_id

Transaction identifier. Refer to

“Overloaded Procedure

Common Arguments”

on page 203 for more details.

bfm_id

BFM identifier. Refer to

“Overloaded Procedure Common

Arguments”

on page 203 for more details.

path_id

(Optional) Parallel process path identifier:

AXI_PATH_0
AXI_PATH_1
AXI_PATH_2
AXI_PATH_3
AXI_PATH_4

Refer to

“Overloaded Procedure Common Arguments”

on

page 203 for more details.

tr_if

Transaction signal interface. Refer to

“Overloaded

Procedure Common Arguments”

on page 203 for more

details.

Returns

None

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