Altera Mentor Verification IP Altera Edition AMBA AXI3/4TM - Manual (Page 671)

VHDL Tutorials
Verifying a Master DUT
Mentor VIP AE AXI3/4 User Guide, V10.2b 651
September 2013
handle_response
The handle_response process sends a response back to the master to complete a write
transaction. It uses unique path and queue identifiers to work concurrently with other processes.
In a loop, the pop_transaction_id() procedure call returns the transaction_id from the queue for
the slave BFM, indexed by the index argument, as shown in Example 11-40 below. A
write_trans variable is previously defined to hold the transaction_id. If the queue is empty then
push_transaction_id() will block until content is available.
The call to set_wr_resp_valid_delay() sets the BVALID signal delay for the response prior to
calling execute_write_response_phase() to execute the response over the protocol signals.
Example 11-40. handle_response
-- handle_response : write response phase through path 2
-- This method sends the write response phase
process
variable write_trans: integer;
begin
loop
pop_transaction_id(write_trans, AXI4_QUEUE_ID_2, index,
AXI4_PATH_2, axi4_tr_if_2(index));
set_wr_resp_valid_delay(write_trans, AXI4_PATH_2,
axi4_tr_if_2(index));
execute_write_response_phase(write_trans, index, AXI4_PATH_2,
axi4_tr_if_2(index));
tmp_config_num_outstanding_wr_phase :=
tmp_config_num_outstanding_wr_phase - 1;
end loop;
wait;
end process;
handle_write_addr_ready
The handle_write_addr_ready process handles the AWREADY signal for the write address
channel. It uses a unique path identifier to work concurrently with other processes.
The handling of the AWREADY signal begins an ACLK period after the ARESETn signal is
inactive, as shown in
Example 11-41 below. In a loop, the AWREADY signal is deasserted using
the nonblocking call to the execute_write_addr_ready() procedure and blocks for a write
channel address phase to occur with a call to the blocking get_write_addr_cycle() procedure. A
received write address phase indicates that the AWVALID signal has been asserted, triggering
the starting point for the delay of the AWREADY signal by the number of ACLK cycles defined
by
m_wr_addr_phase_ready_delay . Another call to the execute_write_addr_ready() procedure
to assert the AWREADY signal completes the AWREADY handling.