Cirrus Logic EP93xx - Manual (Page 123)

DS785UM1 4-5
Copyright 2007 Cirrus Logic
Boot ROM
EP93xx User’s Guide
4
4
4
Note: ASYNC boot mode is the preferred boot mode type for new designs.
Table 4-1. Boot Configuration Options
EECLK EEDAT BOOT1 BOOT0 ASDO CSn[7:6] Boot Configuration
0 1 0 0 1
0 0
0 1
1 0
1 1
External boot using Sync boot mode and SDCSn3.
The media type must be either SyncROM or
SyncFLASH. The selection of the bus width is
determined by latched CSn[7:6] value:
16-bit
16-bit
32-bit
32-bit
0 1 0 0 0
0 0
0 1
1 0
1 1
External boot using Async boot mode and CSn0. The
selection of the bus width is determined by latched
CSn[7:6]
value:
8-bit
16-bit
32-bit
32-bit
1 1 0 1 x xx Internal boot from UART1.
1 1 0 0 x xx Internal SPI boot if HeaderID is found.
1 1 0 0 1
0 0
0 1
1 0
1 1
Internal boot using SYNC boot mode at the chip select
where the HeaderID exists. The selection of the bus
width is determined by latched CSn[7:6] value:
16-bit
16-bit
32-bit
32-bit
See memory map in
Table 2-7 on page 2-16 for SYNC
boot mode.
1 1 0 0 0
0 0
0 1
1 0
1 1
Internal boot using ASYNC boot mode at the chip
select where the HeaderID exists. The selection of the
bus width is determined by latched CSn[7:6] value:
8-bit
16-bit
32-bit
32-bit
See memory map in
Table 2-7 on page 2-16 for
ASYNC boot mode.