Cirrus Logic EP93xx - Manual (Page 7)

DS785UM1
©
Copyright 2007 Cirrus Logic, Inc. vii
EP93xx User’s Guide
8.6.4 Block Copy Function......................................................................................................8-18
8.6.4.1 Example of Block Copy................................................................................8-21
8.7 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-22
Chapter 9. 1/10/100 Mbps Ethernet LAN Controller ........................................... 9-1
9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-1
9.1.1 Detailed Description ........................................................................................................9-1
9.1.1.1 Host Interface and Descriptor Processor .......................................................9-1
9.1.1.2 Reset and Initialization...................................................................................9-2
9.1.1.3 Power-down Modes .......................................................................................9-2
9.1.1.4 Address Space ..............................................................................................9-2
9.1.2 MAC Engine ....................................................................................................................9-3
9.1.2.1 Data Encapsulation........................................................................................9-3
9.1.3 Packet Transmission Process .........................................................................................9-5
9.1.3.1 Carrier Deference ..........................................................................................9-5
9.1.4 Transmit Back-Off............................................................................................................9-7
9.1.4.1 Transmission .................................................................................................9-7
9.1.4.2 The FCS Field................................................................................................9-7
9.1.4.3 Bit Order ........................................................................................................9-8
9.1.4.4 Destination Address (DA) Filter .....................................................................9-8
9.1.4.5 Perfect Address Filtering ...............................................................................9-8
9.1.4.6 Hash Filter .....................................................................................................9-9
9.1.4.7 Flow Control.................................................................................................9-10
9.1.4.8 Receive Flow Control...................................................................................9-10
9.1.4.9 Transmit Flow Control..................................................................................9-10
9.1.4.10 Rx Missed and Tx Collision Counters ........................................................9-11
9.1.4.11 Accessing the MII ......................................................................................9-11
9.2 Descriptor Processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-13
9.2.1 Receive Descriptor Processor Queues .........................................................................9-13
9.2.2 Receive Descriptor Queue ............................................................................................9-13
9.2.3 Receive Status Queue...................................................................................................9-16
9.2.3.1 Receive Status Format ................................................................................9-18
9.2.3.2 Receive Flow ...............................................................................................9-21
9.2.3.3 Receive Errors .............................................................................................9-22
9.2.3.4 Receive Descriptor Data/Status Flow ..........................................................9-23
9.2.3.5 Receive Descriptor Example .......................................................................9-24
9.2.3.6 Receive Frame Pre-Processing ...................................................................9-25
9.2.3.7 Transmit Descriptor Processor Queues.......................................................9-26
9.2.3.8 Transmit Descriptor Queue..........................................................................9-26
9.2.3.9 Transmit Descriptor Format .........................................................................9-28
9.2.3.10 Transmit Status Queue ..............................................................................9-30
9.2.3.11 Transmit Status Format .............................................................................9-32
9.2.3.12 Transmit Flow ............................................................................................9-34
9.2.3.13 Transmit Errors ..........................................................................................9-35
9.2.3.14 Transmit Descriptor Data/Status Flow .......................................................9-36
9.2.4 Interrupts .......................................................................................................................9-37
9.2.4.1 Interrupt Processing.....................................................................................9-37
9.2.5 Initialization....................................................................................................................9-37
9.2.5.1 Interrupt Processing.....................................................................................9-38
9.2.5.2 Receive Queue Processing .........................................................................9-38
9.2.5.3 Transmit Queue Processing ........................................................................9-38
9.2.5.4 Other Processing .........................................................................................9-38
9.2.5.5 Transmit Restart Process ............................................................................9-39
9.3 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-40