Cirrus Logic EP93xx - Manual (Page 347)

DS785UM1 9-45
Copyright 2007 Cirrus Logic
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
9
9
9
Soft Reset:
0x0000_0000
Definition:
Transmit Control Register.
Bit Descriptions:
RSVD: Reserved. Unknown During Read.
DefDis: 2-part DefDis. Before a transmission can begin, the MAC
follows a deferral procedure. With the 2-part DefDis bit
clear, the deferral is the standard two-part deferral as
defined in ISO/IEC 8802-3 paragraph 4.2.3.2.1. With the
2-part DefDis bit set, the two-part deferral is disabled. See
Transmit Back-Off paragraph.
MBE: ModBackoff Enable. When clear, the ISO/IEC standard
backoff algorithm is used. When set, the Modified Backoff
algorithm is used, which delays longer after each of the
first three Tx collisions.
ICRC: Inhibit CRC. When this bit is set, there will be no CRC
appended to transmit frames. If the Abort Frame bit is set
in the transmit descriptor for a frame, the frame will be
terminated with a bad CRC.
TxPD: Tx Pad Disable. When this bit is set, the MAC will not pad
the frame to the legal minimum size (64 bytes). If clear, the
MAC will pad the frame to the minimum legal frame size if
the supplied length is less than 64 bytes. The padded
characters will be the last supplied character in the frame,
repeated.
OColl: One Collision. When this bit is set, no attempt is made to
resend frames in the event of a collision.
SP: Send Pause. When set by the host, this bit causes a
pause frame to be transmitted at the earliest opportunity.
This is at the end of the current frame, if one is already in
progress. This bit will remain set until the transmission of
the frame has started. The pause frame is comprised of
the following elements:
Destination Address Individual Address number 6
Source Address Individual Address number 1
Type Field Type Field defined in the
Flow Control Format register0
Opcode 0x0001
Pause Time Pause Field defined in the
Flow Control Format register
Pad fill