Cirrus Logic EP93xx User Manual
Page 95
DS785UM1
3-25
Copyright 2007 Cirrus Logic
MaverickCrunch Co-Processor
EP93xx User’s Guide
3
3
3
Move Lower Half Double Precision Float from MaverickCrunch to ARM
Description:
Moves the lower half of a double precision floating point value stored in a
MaverickCrunch register into an ARM register.
Mnemonic:
CFMVRDL<cond> Rd, CRn
Bit Definitions:
Rd:
Destination ARM register
CRn: Source
register
Move Upper Half Double Precision Float from ARM to MaverickCrunch
Description:
Moves the upper half of a double precision floating point value from an ARM
register into the upper half of a MaverickCrunch register.
Mnemonic:
CFMVDHR<cond> CRn, Rd
Bit Definitions:
CRn: Destination
register
Rd:
Source ARM register
Move Upper Half Double Precision Float from MaverickCrunch to ARM
Description:
Moves the upper half of a double precision floating point value stored in a
MaverickCrunch register into an ARM register.
Mnemonic:
CFMVRDH<cond> Rd, CRn
Bit Definitions:
Rd:
Destination ARM register
CRn: Source
register
31:28
27:24
23:22
21
20
19:16
15:12
11:8
7:5
4
3:0
cond
1 1 1 0
0 0
0
1
CRn
Rd
0 1 0 0
0 0 0
1
CRm
31:28
27:24
23:22
21
20
19:16
15:12
11:8
7:5
4
3:0
cond
1 1 1 0
0 0
0
0
CRn
Rd
0 1 0 0
0 0 1
1
CRm
31:28
27:24
23:22
21
20
19:16
15:12
11:8
7:5
4
3:0
cond
1 1 1 0
0 0
0
1
CRn
Rd
0 1 0 0
0 0 1
1
CRm