Cirrus Logic EP93xx - Manual (Page 432)

10-38 DS785UM1
Copyright 2007 Cirrus Logic
DMA Controller
EP93xx User’s Guide
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CurrentState: Indicates the states that the M2M Channel Control FSM
and M2M Buffer FSM are currently in:
CurrentState[2:0] - These indicate the state of M2M
Channel Control FSM:
000 - DMA_IDLE
001 - DMA_STALL
010 - DMA_MEM_RD
011 - DMA_MEM_WR
100 - DMA_BWC_WAIT
CurrentState[4:3] - These indicate the state of M2M Buffer
FSM:
00 - DMA_NO_BUF
01 - DMA_BUF_ON
10 - DMA_BUF_NEXT
DONE: Transfer completed successfully. The transfer is
terminated on the occurrence of DEOT being asserted by
the peripheral or the byte count expiring, whichever
happens sooner. When a transfer completes, software
must clear the Interrupt.DONEInt bit before
reprogramming the DMA, by writing either “0” or “1” to this
bit. The DMA will ignore any more DREQs that it receives
from the external device (if operating in external peripheral
mode) until such time that software clears the DONE
interrupt and reprograms the DMA with new BCRx values,
and this even if the DMA interrupt is disabled.
TCS: Terminal Count status. This status bit reflects whether or
not the actual byte count has reached the programmed
limit for buffer descriptor “0” or “1” respectively:
00 - Terminal Count has not been reached for either buffer
descriptor 1 or 0.
01 - Terminal Count has not been reached for buffer 1 and
has been reached for buffer descriptor 0.
10 - Terminal Count has been reached for buffer 1 and has
not been reached for buffer descriptor 0.
11 - Terminal Count has been reached for both buffer
descriptors.
The TCS status bit for a buffer descriptor is cleared when
the BCR register of that buffer descriptor has been
programmed with a new value.