Cirrus Logic EP93xx User Manual
Page 365
DS785UM1
9-63
Copyright 2007 Cirrus Logic
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
9
9
9
Definition:
Global Interrupt Status Register
Bit Descriptions:
RSVD:
Reserved. Unknown During Read.
INT:
Global interrupt bit. This bit is set whenever the MACint
signal to the interrupt controller is active. Writing a one to
this bit location will clear this bit until a new interrupt
condition occurs.
GlIntMsk
Address:
0x8001_0064 - Read/Write
Chip Reset:
0x0000_0000
Soft Reset:
0x0000_0000
Definition:
Global Interrupt Mask Register. This register is used to mask the GlIntSts bit,
to allow of block interrupts to the processor.
Bit Descriptions:
RSVD:
Reserved. Unknown During Read.
INT:
Global interrupt mask bit. When set, any interrupt enabled
by the Interrupt Enable Register will set the Global
Interrupt Status interrupt bit. When clear, no interrupts will
reach the processor.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RSVD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
INT
RSVD