Cirrus Logic EP93xx - Manual (Page 527)

DS785UM1 14-5
Copyright 2007 Cirrus Logic
UART1 With HDLC and Modem Control Signals
EP93xx User’s Guide
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14
14.2.1.10 Synchronizing Registers and Logic
The UART supports both asynchronous and synchronous operation of the clocks, PCLK and
UARTCLK. Synchronization registers and handshaking logic have been implemented, and
are active at all times. This has a minimal impact on performance or area. Synchronization of
control signals is performed on both directions of data flow, that is, from the PCLK to the
UARTCLK domain and from the UARTCLK domain to the PCLK.
14.2.2 UART Operation
Control data is written to the UART line control register, UARTLCR. This register is 23 bits
wide internally, but is externally accessed through the AMBA APB bus by three 8-bit wide
register locations, UARTLCR_H, UARTLCR_M and UARTLCR.L.
UARTLCR defines the baud rate divisor and transmission parameters, word length, buffer
mode, number of transmitted stop bits, parity mode and break generation.
The baud rate divisor is a 16-bit number used by the baud rate generator to determine the bit
period. The baud rate generator contains a 16-bit down counter, clocked by the UART
reference clock. When the value of the baud rate divisor has decremented to zero, the value
of the baud rate divisor is reloaded into the down counter, and an internal clock enable signal,
Baud16, is generated. This signal is then divided by 16 to give the transmit clock. A low
number in the baud rate divisor gives a short bit period and vice versa.
Data received or transmitted is stored in two 16-byte FIFOs, though the receive FIFO has an
extra three bits per character for status information.
For transmission, data is written into the transmit FIFO. This causes a data frame to start
transmitting with the parameters indicated in UARTLCR. Data continues to be transmitted
until there is no data left in the transmit FIFO. The BUSY signal goes HIGH as soon as data
is written to the transmit FIFO (that is, the FIFO is non-empty) and remains asserted HIGH
while data is being transmitted. BUSY is negated only when the transmit FIFO is empty, and
the last character has been transmitted from the shift register, including the stop bits. BUSY
can be asserted HIGH even though the UART may no longer be enabled.
When the receiver is idle (UARTRXD continuously 1, in the marking state) and a LOW is
detected on the data input (a start bit has been received), the receive counter, with the clock
enabled by Baud16, begins running and data is sampled on the eighth cycle of that counter
(half way through a bit period).
The start bit is valid if UARTRXD is still LOW on the eighth cycle of Baud16, otherwise a false
start bit is detected and it is ignored.
If the start bit was valid, successive data bits are sampled on every 16th cycle of Baud16 (that
is, one bit period later) according to the programmed length of the data characters. The parity
bit is then checked if parity mode was enabled.
Lastly, a valid stop bit is confirmed if UARTRXD is HIGH, otherwise a framing error has
occurred. When a full word has been received, the data is stored in the receive FIFO, with
any error bits associated with that word (see
Table 14-1 ).