Cirrus Logic EP93xx - Manual (Page 373)

DS785UM1 9-71
Copyright 2007 Cirrus Logic
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
9
9
9
RxAct: Receive Active. When this bit is set, the channel is active
and may be in the process of transferring receive data.
Following a RxDisable Command (Bus Master Control),
when transfers have been halted, this bit is cleared.
QID: Queue ID. The queue ID reflects the current or last DMA
queue active on the AHB bus. When an AHB error halts
DMA operation, this field may be used to determine the
queue that caused the error.
ID Type of transfer
000 - Receive data
001 - Transmit data
010 - Receive status
011 - Transmit status
100 - Receive descriptor
101 - Transmit descriptor
Descriptor Processor Receive Registers
RXDQBAdd
Address:
0x8001_0090 - Read/Write
Chip Reset:
0x0000_0000
Soft Reset:
Unchanged
Definition:
Receive Descriptor Queue Base Address register. The Receive Descriptor
Queue Base Address defines the system memory address of the receive
descriptor queue, this address is used by the MAC to reload the Receive
Current Descriptor Address whenever the end of the descriptor queue is
reached. The base address should be set at initialization time and must be set
to a word aligned memory address.
Bit Descriptions:
RDBA: Receive Descriptor Base Address.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDBA
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDBA