Cirrus Logic EP93xx User Manual
Page 785
DS785UM1
27-15
Copyright 2007 Cirrus Logic
IDE Interface
EP93xx User’s Guide
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DMA controller. A write by the host during MDMA data-out operation will
erroneously interfere with the MDMA state machine. Any read will return zero.
Bit Descriptions:
IDEDD:
IDE output data in the output buffer in MDMA mode.
IDEMDMADataIn
Address:
0x800A_001C - Read Only (should be read by the DMA controller only)
Default:
0x0000_0000
Definition:
In MDMA data-in operations, this register contains the data in the input buffer
just transferred from the device. The data is read from this register by the DMA
controller. This register should only be addressed and read by the DMA
controller. A read by the host during MDMA data-in operation will erroneously
interfere with the MDMA state machine. Any write is ignored.
Bit Descriptions:
IDEDD:
IDE input data in the input buffer in MDMA mode.
IDEUDMADataOut
Address:
0x800A_0020 - Write Only (should be written by the DMA controller only)
Default:
0x0000_0000
Definition:
In UDMA data-out operations, this register contains the data at the tail of the
output buffer to be written by the DMA controller. This register should only be
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IDEDD
15
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0
IDEDD
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IDEDD
15
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1
0
IDEDD