Cirrus Logic EP93xx User Manual
Page 788
27-18
DS785UM1
Copyright 2007 Cirrus Logic
IDE Interface
EP93xx User’s Guide
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7
2
7
27
IDEUDMADebug
Address:
0x800A_002C - Read/Write
Default:
0x0000_0000
Definition:
Debug register to reset some internal signals in the UDMA state machine for
debug purpose.
Bit Descriptions:
RSVD:
Reserved. Unknown during read, ignored during writes.
RWOE:
Reset UDMA write data-out error.
RWPTR:
Reset UDMA write buffer pointer to 0.
RWDR:
Reset UDMA write DMA request.
RROE:
Reset UDMA read data-in error.
RRPTR:
Reset UDMA read buffer pointer to 0.
RRDR:
Reset UDMA read DMA request.
IDEUDMAWrBufSts
Address:
0x800A_0030 - Read Only
Default:
0x0000_0100
Definition:
Status register for UDMA write buffer.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RSVD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RSVD
RRDR
RRPTR
RROE
RWDR
RWPTR
RWOE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
CRC
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RSVD
FULL
NFULL
HOM
EMPTY
TPTR
HPTR