Cirrus Logic EP93xx User Manual
Page 284
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DS785UM1
Copyright 2007 Cirrus Logic
Graphics Accelerator
EP93xx User’s Guide
8
8
8
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E. Write the desired value to the HEIGHT field in the
register,
where HEIGHT = the height in lines of the image that is to be copied minus 1.
For example, a 20-pixels x 10-lines image has a height of 10 lines. So, HEIGHT =
10 - 1 = 9 = 0x9.
F. The
register must be cleared to 0x0. This action clears out the
previous graphics instruction. The EOI bit field must be cleared to ‘0’ regardless of
the interrupt enable status.
The PACKD bit must be configured to indicate if the image to be copied has the
same size for the source and the destination. Setting the PACKD bit allows transfers
from images that are packed into whole word areas.
The P bits must be configured for the BPP depth of the image to be copied.
When using the AND/OR/XOR mask function, the M bits must be configured for the
appropriate function.
When using the AND/OR/XOR destination function, the D bits must be configured
for the appropriate function.
When using transparency, the TRANS bit must be enabled to ‘1’. This allows data
from the source to be compared with the transparency pixel pattern to determine if
the destination pixel is to be modified before it is written. Without this bit enabled, a
direct block copy would occur.
The SYDIR, SXDIR and DYDIR, DXDIR direction bits must be configured. These
bits control the direction for the line accumulator, Y, and the word/pixel counter, X. In
a left to right and top to bottom transfer:
(1).if the destination is not exactly the same as the source, or
(2).if the destination partially overlaps the source and has a destination starting
word address greater than the source starting word address, then the source
information may be corrupted before being read. For this condition, the
direction bits for the transfer must be changed from left to right and top to
bottom to right to left and bottom to top.
Note: Setting the source direction bits different from the destination direction bits is illegal and
will have unpredictable results.
G. The INTEN bit must configured to enable or disable an interrupt signal to the ARM
Core that occurs upon completion of the acceleration function.
H. After Step G is complete, write EN = ‘1’ to start the Block Copy function.
I. Wait for an interrupt or poll for EN = ‘0’. When the EN bit is cleared to ‘0’, the Block
Copy function sequence is done.