Cirrus Logic EP93xx - Manual (Page 546)

14-24 DS785UM1
Copyright 2007 Cirrus Logic
UART1 With HDLC and Modem Control Signals
EP93xx User’s Guide
1
4
1
4
14
CTS: Clear To Send status. This bit is the complement of the
UART clear to send (nUARTCTS) modem status input.
That is, the bit is 1 when the modem status input is 0.
UART1IntIDIntClr
Address:
0x808C_001C - Read/Write
Default:
0x0000_0000
Definition:
UART Interrupt Identification and Interrupt Clear Register.
Bit Descriptions:
RSVD: Reserved. Unknown During Read.
RTIS: Receive Timeout Interrupt Status. This bit is set to 1 if the
UARTRTINTR receive timeout interrupt is asserted. This
bit is cleared when the receive FIFO is empty or the
receive line goes active.
TIS: Transmit Interrupt Status.
1 - The UARTTXINTR transmit interrupt is asserted, which
occurs when the transmit FIFO is not full.
0 - The transmit FIFO is full.
RIS: Receive Interrupt Status.
1 - The UARTRXINTR receive interrupt is asserted, which
occurs when the receive FIFO is not empty.
0 - The receive FIFO is empty.
MIS: Modem Interrupt Status. This bit is set to 1 if the
UARTMSINTR modem status interrupt is asserted. This
bit is cleared by writing any value to this register.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD RTIS TIS RIS MIS