Cirrus Logic EP93xx - Manual (Page 381)

DS785UM1 9-79
Copyright 2007 Cirrus Logic
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
9
9
9
Chip Reset:
0x0000_0000
Soft Reset:
Unchanged
Definition:
Receive Header Length register. The Receive Header Length registers are
used to generate status after receiving a specific portion of a receive frame.
When the number of bytes specified in either register has been transferred to
the external data buffer, an appropriate status is generated. The status for a
receive header will reflect the number of bytes transferred for the current
frame, the address match field will be valid, and the other status bits will be set
to zero. A status will only be generated for header length 2 if the length is
greater than that specified for header length 1.
Bit Descriptions:
RSVD: Reserved. Unknown During Read.
RHL2: Receive Header Length 2.
RHL1: Receive Header Length 1.
Descriptor Processor Transmit Registers
TXDQBAdd
Address:
0x8001_00B0 - Read/Write
Chip Reset:
0x0000_0000
Soft Reset:
Unchanged
Definition:
Transmit Descriptor Base Address register. The Transmit Descriptor Queue
Base Address defines the system memory address of the transmit descriptor
queue. This address is used by the MAC to reload the Transmit Current
Descriptor Address whenever the end of the descriptor queue is reached. The
base address should be set at initialization time and must be set to a word
aligned memory address.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TDBA
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDBA