Cirrus Logic EP93xx - Manual (Page 405)

DS785UM1 10-11
Copyright 2007 Cirrus Logic
DMA Controller
EP93xx User’s Guide
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No data transfers occur in this state.
10.1.10.1.3 DMA_MEM_RD
The DMA M2M Control FSM enters the DMA_MEM_RD state when a M2M channel has
received a software trigger to begin a transfer, that is, the START bit is set (CONTROL[4])
and CONTROL.TM = “00”; or when IDE or SSP asserts its request line and CONTROL.TM =
“01” or “10”; or when an external device asserts its DREQ o/p to the DMA and CONTROL.TM
= “01” or “10”. At least one of the BCRx registers must contain a valid value, otherwise the
DMA stays in the DMA_STALL state. For software triggered mode a valid BCR value is any
non-zero value. For external DMA mode a valid BCR value depends on the peripheral width
(programmed via the PW bits of the CONTROL register). For word/half-word/byte-wide
peripherals the BCR value must be greater than or equal to four/two/one respectively.
The DMA M2M Control FSM enters the DMA_MEM_RD state when a memory write transfer
has finished and the BCR register is still not equal to zero, that is, more data needs to be
transferred from memory-to-memory. For external bus and IDE/SSP transfers, BCR not-
equal-to 0 must be qualified with a DREQ before the DMA_MEM_RD state is entered again.
The DMA M2M Control FSM enters the DMA_MEM_RD state on exit from the
DMA_BWC_WAIT state, if all the data present in the data bay had been transferred to
memory when DMA_BWC_WAIT state was entered.
The DMA M2M Control FSM stays in this state until the data transfer from memory has
completed for software trigger mode, that is, the data bay is filled with 16 bytes (or less
depending on transfer size and BCR value etc.).
The DMA M2M Control FSM enters the DMA_MEM_RD state when the BCR register is equal
to zero for the current buffer, and the other buffer descriptors BCR register has been
programmed non-zero. DMA will proceed to do a memory read using the new buffer and the
NFB interrupt is generated, if enabled.
Data transfers from memory or external bus/device (depending on the CONTROL.TM bits),
occur in this state.
10.1.10.1.4 DMA_MEM_WR
The DMA M2M Control FSM enters the DMA_MEM_WR state when a memory read transfer
has completed.
The DMA M2M Control FSM enters the DMA_MEM_WR state on exit from the
DMA_BWC_WAIT state, if all the data present in the data bay had not been transferred to
memory when DMA_BWC_WAIT state was entered.
The DMA M2M Control FSM stays in this state until the data transfer to memory has
completed, that is, the data bay is emptied.
Data transfers, to memory or external peripheral (depending on the CONTROL.TM bits),
occur in this state.