Cirrus Logic EP93xx - Manual (Page 344)

9-42 DS785UM1
Copyright 2007 Cirrus Logic
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
9
9
9
Chip Reset:
0x0000_0x0x
Rx Reset:
0x0000_0000
Soft Reset:
0x0000_0000
Definition:
Receiver Control Register. The Receive Control register is reset by Rx Reset
signal generated by holding the TESTSELn pin low. The same signal is also
used to reset the receive MAC. The purpose of having a separate reset signal
is to be able to avoid resetting the receive MAC when the AHB bus is in a
powered down state (RESET active), and wake-up frames need to be
detected.
Bit Descriptions:
RSVD: Reserved. Unknown During Read.
Note: The IA field of the table means the same Individual Addresses as RxFCE, that is, IA0
implies RxFCE0 and IA1 implies RxFCE1
PauseA: Pause Accept. When set, Pause frames are passed on to
the Host as regular frames. When clear, the frames are
discarded. The handling of MAC Control frames depends
on the Pause Accept bit as well as the appropriate
Individual Accept and RxFlow Control Enable bits, as
follows.
Table 9-4. Individual Accept, RxFlow Control Enable and Pause Accept Bits
IA[1:0]
Individu
al
Accept
RxFCE[1:
0]
Receive
Flow
Control
Enable
PauseA
Pause
Accept
Action
0 X X Frame discarded (do not pass the address filter)
1 1 0
MAC Control frames are recognized, flow control action taken,
and frames not passed to host. Non pause MAC Control
frames are passed on to host.
1 1 1
MAC Control frames are recognized, flow control action taken,
and all MAC control frames are passed on to host.
1 0 X
MAC Control frames are not distinguished from other frame
types, all frames passed on to host.