Cirrus Logic EP93xx User Manual
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DS785UM1
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Copyright 2007 Cirrus Logic
IrDA
EP93xx User’s Guide
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WST:
Width Status.
00 - All four bytes in receive buffer are valid.
01 - Least significant byte is valid only.
10 - Least significant two bytes are valid only.
11 - Least significant three bytes are valid only.
FRE:
FIR Framing Error.
0 - No framing errors encountered in the receipt of FIR
data.
1 - Framing error occurred, FIR preamble followed by
something other than another preamble or FIR start flag.
The data in the buffer is invalid.
ROR:
Receive buffer Overrun.
0 - Receive buffer has not experienced an overrun.
1 - Receive logic attempted to place data into receive
buffer while it was full. The next data value in the buffer is
the last piece of “good” data before the buffer was overrun.
CRE:
CRC Error.
0 - No CRC check errors encountered in the data.
1 - CRC calculated on the incoming data does not match
CRC value contained within the received frame.
RAB:
Receiver Abort.
0 - No abort has been detected for the incoming frame.
1 - Abort detected during receipt of the incoming frame,
EOF bit set in receive buffer next to the last piece of
“good” data received before abort.
IrData
Address:
0x808B_0010 - Read/Write
Default:
0x0000_0000
Definition:
IrDA Data Register. Provides access to the transmit and receive buffers used
by the MIR and FIR interfaces.
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DATA
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DATA