Cirrus Logic EP93xx - Manual (Page 240)

7-58 DS785UM1
Copyright 2007 Cirrus Logic
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
7
7
7
Writing a Dual Scan value to this bit selects whether the
display is used in single scan mode, or dual scan mode
where the display is divided into a ‘top’ half and a ‘bottom’
half. In dual scan mode, the video frame buffer in SDRAM
must be organized such that ‘top’ and ‘bottom’ pixels
alternate in consecutive locations. ‘Top’ and ‘bottom’ pixels
are fetched and input to the Raster Engine’s video
pipeline. The output shifter is set up to drive the top and
bottom half screen data at the same time. Dual scan mode
is intended for passive matrix LCD screens that require
both halves of the screen to be scanned out at the same
time. However, dual scan mode could also be used to
drive two separate synchronized displays, each with
different data.
0 - Single Scan (full page)
1 - Dual Scan (two half pages)
C: Color - Read/Write
The Color Mode is specified by selecting a value from
Table 7-13 and writing it to this field.
M: Mode - Read/Write
The Blink Mode is specified by selecting a value from
Table 7-14 and writing it to this field.
Table 7-13. Color Mode Definition Table
C3 C2 C1 C0 Color Mode
0 0 0 0 Use LUT Data
0 1 0 0 Triple 8 bits per channel
0 1 0 1 16-bit 565 color mode
X 1 1 0 16-bit 555 color mode
1 X X X Grayscale Palettes Enabled
Table 7-14. Blink Mode Definition Table
M3 M2 M1 M0 Blink Mode
0 0 0 0 Blink Mode Disabled
0 0 0 1 Pixels ANDed with Blink Mask
0 0 1 0 Pixels ORed with Blink Mask
0 0 1 1 XORed with Blink Mask
0 1 0 0 Blink to background register Value