Blinkpattrn – Cirrus Logic EP93xx User Manual
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DS785UM1
Copyright 2007 Cirrus Logic
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
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Bit Descriptions:
RSVD:
Reserved - Unknown during read
MASK:
Mask - Read/Write
The Blink Mask value that is written to this field is logical
ANDed, ORed, or XORed with the pixel data that
addresses the LUT. The mask allows a blinking pixel to
jump from the normal color definition location to a blink
color definition location in the look-up-table.
The logical operator is selected by writing to the M field in
the
register. The functions of the BlinkMask
AND/OR/XOR operation can be viewed as:
ANDing modifies the LUT address by clearing bits
ORing modifies the LUT address by setting bits
XORing modifies the LUT address by inverting bits
BlinkPattrn
Address: 0x8003_0048
Default: 0x0000_0000
Definition: Blink Pattern register
This register is used in conjunction with the
which pixels that are fetched from SDRAM are blink pixels (see
).
Bit Descriptions:
RSVD:
Reserved - Unknown during read
PATRN:
Pattern - Read/Write
The pixel value is first operated on by the Mask field in the
register. The result is then compared to the
blink pattern value that is written to this PATRN field. If the
comparison results in a match, the pixel is validated as a
blink pixel.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RSVD
PATRN
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PATRN