Pixelmode, Regi – Cirrus Logic EP93xx User Manual
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Copyright 2007 Cirrus Logic
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
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This field should be written with a value that specifies the
number of words that the FIFO empties before the FIFO
requests that it be refilled. Values greater than 16 should
be used with extreme caution as they can cause the
Raster Engine to underflow, causing video jitter or other
visual defects.
PixelMode
Address: 0x8003_0054
Default: 0x0000_0000
Definition: Pixel Mode register
Bit Descriptions:
RSVD:
Reserved - Unknown during read
0:
Must be written as ‘0’
TRBSW:
Two and Two-Thirds Red/Blue Swap - Read/Write
Writing a Two and two-thirds Red/Blue Swap value to this
bit selects the ordering of Red and Blue pixels for data
shifted displays:
0 - Normal: Blue is the low order bits followed by green
and red
1 - Reverse: Red is low order bits followed by green and
blue
DSCAN:
Dual Scan - Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RSVD
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TRBSW
DSCAN
C
M
S
P