Cirrus Logic EP93xx User Manual
Page 96
3-26
DS785UM1
Copyright 2007 Cirrus Logic
MaverickCrunch Co-Processor
EP93xx User’s Guide
3
3
3
Move Lower Half 64-bit Integer from ARM to MaverickCrunch
Description:
Moves the lower half of a 64-bit integer from an ARM register into the lower
half of a MaverickCrunch register and sign extend it.
Mnemonic:
CFMV64LR<cond> CRn, Rd
Bit Definitions:
CRn: Destination
register
Rd:
Source ARM register
Move Lower Half 64-bit Integer from MaverickCrunch to ARM
Description:
Moves the lower half of a 64-bit integer stored in a MaverickCrunch register
into an ARM register.
Mnemonic:
CFMVR64L<cond> Rd, CRn
Bit Definitions:
Rd:
Destination ARM register
CRn: Source
register
Move Upper Half 64-bit Integer from ARM to MaverickCrunch
Description:
Moves the upper half of a 64-bit integer from an ARM register into the upper
half of a MaverickCrunch register.
Mnemonic:
CFMV64HR<cond> CRn, Rd
Bit Definitions:
CRn: Destination
register
Rd:
Source ARM register
31:28
27:24
23:22
21
20
19:16
15:12
11:8
7:5
4
3:0
cond
1 1 1 0
0 0
0
0
CRn
Rd
0 1 0 1
0 0 0
1
CRm
31:28
27:24
23:22
21
20
19:16
15:12
11:8
7:5
4
3:0
cond
1 1 1 0
0 0
0
1
CRn
Rd
0 1 0 1
0 0 0
1
CRm
31:28
27:24
23:22
21
20
19:16
15:12
11:8
7:5
4
3:0
cond
1 1 1 0
0 0
0
0
CRn
Rd
0 1 0 1
0 0 1
1
CRm