Table 10-8. ppalloc register reset values -30, Currentx – Cirrus Logic EP93xx User Manual
Page 424
10-30
DS785UM1
Copyright 2007 Cirrus Logic
DMA Controller
EP93xx User’s Guide
1
0
1
0
10
CURRENTx
Address:
CURRENT0: Channel Base Address + 0x0028 - Read Only
CURRENT1: Channel Base Address + 0x0038 - Read Only
Definition:
This is the Channel Current Address Register.
Bit Descriptions:
CURRENTx:
Returns the current value of the channel address pointer.
Upon enabling the DMA Channel and writing the BASE
Address Register the contents of this register is loaded
into the CURRENTx register and the x buffer becomes
active. Following completion of a transfer from a buffer, the
post-incremented address is stored in this register so that
a software service routine can detect the point in the buffer
at which transfer was terminated.
M2M Channel Register Map
The DMA Memory Map defines the mapping for the channel registers for each of the 2 M2M
channels that are shown in
, the M2M Channel Register Map. This mapping is
common for each channel thus offset addresses are shown.
Note that M2M Channel 0 is dedicated to servicing External Device 0, and M2M Channel 1 is
dedicated to servicing External Device 1 (when in external DMA transfer mode).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
CURRENTx
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CURRENTx
Table 10-8. PPALLOC Register Reset Values
Offset
Name
Access
Bits
Reset Value
Channel Base Address + 0x0000
CONTROL
R/W
32
0
Channel Base Address + 0x0004
INTERRUPT
R/W TC*
3
0
Channel Base Address + 0x0008
Reserved
Channel Base Address + 0x000C
STATUS
R/W TC*
14
0
Channel Base Address + 0x0010
BCR0
R/W
16
0
Channel Base Address + 0x0014
BCR1
R/W
16
0
Channel Base Address + 0x0018
SAR_BASE0
R/W
32
0
Channel Base Address + 0x001C
SAR_BASE1
R/W
32
0
Channel Base Address + 0x0020
Reserved
Channel Base Address + 0x0024
SAR_CURRENT0
RO
32
0