Figure 9-8. receive status queue -17 – Cirrus Logic EP93xx User Manual
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Copyright 2007 Cirrus Logic
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
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Figure 9-8. Receive Status Queue
Receive status entries are written to the status queue following one of three possible events,
end of header, end of buffer, or end of frame. The status event is always written after the
appropriate data transfer has been made. For example the end of frame status is written after
the last byte of data has been written to the data buffer, not before. The EOF and EOB bits in
the status entry can be used to determine the cause of a status entry.
Receive Status
queue Base
Address (32)
(RxSBA)
Receive Status Queue
bits 31 - 0
Receive Status
Current Address(32)
(RxSCA)
Status (31)
Buffer
Index (15)
R
S
ta
tQ
0
R
S
ta
tQ
1
R
S
ta
tQ
c
c = current frame
Frame
Length (16)
R
S
ta
tQ
c
+
1
R
S
ta
tQ
j
Receive Status
queue Base Length (16)
(RxSBL)
R
P
F
R
P
F
Status (31)
Buffer
Index (15)
Frame
Length (16)
R
P
F
R
P
F
Status (31)
Buffer
Index (15)
Frame
Length (16)
R
P
F
R
P
F
Status (31)
Buffer
Index (15)
Frame
Length (16)
R
P
F
R
P
F
Status (31)
Buffer
Index (15)
Frame
Length (16)
R
P
F
R
P
F