Cirrus Logic EP93xx - Manual (Page 624)

17-28 DS785UM1
Copyright 2007 Cirrus Logic
IrDA
EP93xx User’s Guide
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Bit Descriptions:
DATA: IrDA data word. Values written and sent to the transmit
FIFO. Values read are from the receiver FIFO.
IrDataTail
Address:
0x808B_0014, 0x808B_0018, 0x808B_001C - Write Only
Default:
0x0000_0000
Definition:
IrDA Data Tail Register. This is a 24-bit write only register used for transmitting
frames whose payload data is not an integer multiple of 4 bytes long. The bit
locations are cleared when read by the transmit logic or when the TXE control
bit is clear. The IrData Tail register may be written using one of three
addresses. Bits two and three of the address determine how many bytes
within the word are significant, that is, are intended for transmission. If none of
the address is written, the register remains marked as empty and payload data
will be read by the transmit logic from the 32-bit FIFO only. The status of this
register does not affect the TFS flag, nor does it cause interrupts or DMA
requests to be generated.
Bit Descriptions:
RSVD: Reserved. Unknown During Read.
DATA: IrDA transmit payload data. Write to address 0x014, least
significant byte is transmitted. Write to address 0x018,
least significant two bytes are transmitted. Write to
address 0x01C, least significant three bytes are
transmitted.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA